DocumentCode
903475
Title
A CMOS VAX microprocessor with on-chip cache and memory management
Author
Archer, David W. ; Deverell, David R. ; Fox, Thomas F. ; Gronowski, Paul E. ; Jain, Anil K. ; Leary, Michael ; Miner, Daniel G. ; Olesin, Andrew ; Persels, Shawn D. ; Rubinfeld, Paul I. ; Supnik, Robert M.
Volume
22
Issue
5
fYear
1987
fDate
10/1/1987 12:00:00 AM
Firstpage
849
Lastpage
852
Abstract
A single-chip 32-b microprocessor designed in a 2-μm (drawn) CMOS process with two layers of metal interconnect is described. The microprocessor implements the VAX architecture. A one-transistor dynamic RAM cell is used to build a 1-kbyte instruction and data cache. The chip contains 134000 transistors, is 9.4×9.7 mm/SUP 2/ large, operates at 5.0 V, and dissipates 1.5 W.
Keywords
Buffer storage; CMOS integrated circuits; DEC computers; Microprocessor chips; Storage management; buffer storage; microprocessor chips; storage management; BiCMOS integrated circuits; CMOS technology; Memory management; Microprocessors; Random access memory; Space vector pulse width modulation; Very large scale integration; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052823
Filename
1052823
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