Novel circuit technology for ECL-compatible GaAs static RAMs with small access time scattering

A novel circuit technology has been developed to realize GaAs SRAMs suitable for use in real-system environments. It has achieved Si ECL compatibility through the use of an ECL 100 K-compatible input buffer circuit with on-chip reference compensation. Wide V/SUB th/ tolerance and an improved noise margin have been obtained through the use of a novel normally-on-type circuit called the FET logic with Schottky diode and coupling capacitor (FLSC). Two experimental ECL-compatible GaAs SRAMs (256-word×4-b and 1024-word×4-b) were designed and successfully fabricated using this technology. In the 4 K SRAM, an access time of 2.2-3.0 ns with a power dissipation of 890 mW was achieved and the normal read/write operation at 4-ns cycle time was also confirmed.