Title :
CMOS scan-path IC design for stuck-open fault testability
Author :
Liu, Dick L. ; McCluskey, Edward J.
fDate :
10/1/1987 12:00:00 AM
Abstract :
A design technique which facilitates testing for stuck-open faults in CMOS VLSI circuits with scan paths is described. In this technique, the combinational circuitry is implemented with specially designed gates which can be tested with a simplified two-pattern test for stuck-open faults. The simplified two-pattern test cannot be invalidated by stray circuit delays and it can be applied through the scan path by specially designed shift-register latches (SRLs).
Keywords :
CMOS integrated circuits; Combinatorial circuits; Integrated circuit testing; Integrated logic circuits; Logic design; Logic testing; VLSI; combinatorial circuits; integrated circuit testing; integrated logic circuits; logic design; logic testing; CMOS integrated circuits; Circuit faults; Circuit testing; Combinational circuits; Delay; FETs; Integrated circuit testing; Logic gates; Robustness; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052828
