High-speed operation of upward-injecting transistors by reducing the stored charge

Inverter gates using upward-injecting transistors have been operated with gate delays below 0.4 ns. This fast operation has been achieved by using a resistor in place of the usual p-n-p transistor in merged transistor logic/integrated injection logic (MTL/I/SUP 2/L) gates, to increase pull-up current while reducing capacitance. Capacitance is further reduced by eliminating the lightly doped epi region of the buried emitter and by using self-alignment techniques to reduce junction areas, but without resorting to the special processing needed to provide oxide isolation between the external base and the emitter.