Title :
Threshold-voltage variations in VLSI MOSFETs due to short channel lengths
Author :
Nataraj, B.S. ; Kumar, Rajendra
fDate :
10/1/1987 12:00:00 AM
Abstract :
A simple model is derived for the threshold voltage of a MOSFET in a CMOS n-well or p-well process. The model includes the short-channel effects and considers a Gaussian distribution of the n-type implant in the n-well. An expression is derived based on the charge conservation principle for a case of low drain-source voltage V/SUB DS/, which geometrically takes into account the two-dimensional edge effects. The model is in agreement with the measured threshold voltages of typical CMOS (p-channel) transistors. The model is also in agreement with L.D. Yau´s model (1974) in the limiting case of uniform channel doping.
Keywords :
CMOS integrated circuits; Field effect integrated circuits; Semiconductor device models; VLSI; field effect integrated circuits; semiconductor device models; CMOS process; Doping; Gaussian distribution; Implants; Low voltage; MOSFETs; Semiconductor device modeling; Semiconductor process modeling; Threshold voltage; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052833
