DocumentCode
903986
Title
A ±5-V CMOS analog multiplier
Author
Qin, Shi-cai ; Geiger, Randy L.
Volume
22
Issue
6
fYear
1987
fDate
12/1/1987 12:00:00 AM
Firstpage
1143
Lastpage
1146
Abstract
A four-quadrant CMOS analog multiplier is presented. The device is nominally biased with ±5-V supplies, has identical full-scale single-ended x and y inputs of ±4 V, and exhibits less than 0.5% nonlinear error at 75% of full-scale swing. Operation with supplies as low as ±2.5 V is also possible. A comparison of theoretical and experimental results obtained from fabrication of the multiplier in a 3-μm p-well CMOS process is made.
Keywords
CMOS integrated circuits; Multiplying circuits; multiplying circuits; Bandwidth; CMOS process; Circuits; Electrons; Low voltage; Receivers; Regulators; Resistors; Temperature sensors; Variable structure systems;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052866
Filename
1052866
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