Title :
Storage array and sense/refresh circuit for single-transistor memory cells
Author :
Stein, Karl U. ; Sihling, Aarne ; Doering, Elko
fDate :
10/1/1972 12:00:00 AM
Abstract :
For the cell layout in silicon-gate technology a storage capacitor is proposed that uses a field-induced nonequilibrium inversion layer as an electrode. As a sensitive refresh amplifier a gated flip-flop that can be used for one digit line at each of its two input nodes is presented. Different cells and refresh circuits have been realized in silicon-gate technologies. Cells with an area of 1600 μm/SUP 2/(2.6 mil/SUP 2/) have been successfully operated with a READ/WRITE cycle time of 350 ns (storage capacitance 0.134 pF, digit line capacitance 0.32 pF for 64 cells per line or 128 cells per amplifier).
Keywords :
Amplifiers; Field effect transistors; Semiconductor storage devices; Semiconductor storage systems; amplifiers; field effect transistors; semiconductor storage devices; semiconductor storage systems; Capacitance; Circuit noise; Contacts; Costs; Electrodes; Flip-flops; Helium; MOS capacitors; MOSFETs; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1972.1052889
