Prediction of hysteresis losses produced by distorted flux in low-loss silicon-iron transformer core laminations

A digital method for predicting the hysteresis losses in low-loss silicon-iron laminations, as used in transformer cores, with distorted supply voltages, is presented. The method uses a model based on a piecewise linearisation technique to simulate steady-state B/H characteristics for such materials. Major and minor loop areas computed from simulated B/H characteristics are used to estimate the hysteresis and eddy current components of the measured no-load loss and the respective components had the supply voltage remained sinusoidal. The method neither requires any assumption regarding distribution of these losses in the iron loss nor uses any empirical correction factor for the prediction of sinusoidal losses. Computed values are in good agreement with experimental results. It is possible to use the method for correcting the iron losses measured in a transformer when the supply voltage is distorted