Title :
Random pattern testability of delay faults
Author :
Savir, Jacob ; Mcanney, William H.
Author_Institution :
IBM, Poughkeepsie, NY, USA
fDate :
3/1/1988 12:00:00 AM
Abstract :
In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. Here, the capability of random patterns to detect slow paths in combinational logic is analyzed. Formulas that relate the length of the test to the desired test quality are derived
Keywords :
combinatorial circuits; logic testing; combinational logic networks; delay faults; latches; random pattern testability; system clocks; Circuit faults; Circuit testing; Clocks; Delay effects; Fault detection; Logic circuits; Logic design; Logic testing; Manufacturing; Propagation delay;
Journal_Title :
Computers, IEEE Transactions on
