Architecture of the Pentium microprocessor

Author

Alpert, Donald ; Avnon, Dror

Author_Institution

Intel Corp., Santa Clara, CA, USA

Volume

13

Issue

3

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

11

Lastpage

21

Abstract

The techniques of pipelining, superscalar execution, and branch prediction used in the Pentium CPU, which integrates 3.1 million transistors in 0.8- mu m BiCMOS technology, are described. The technology improvements associated with the three most recent microprocessor generations are outlined. The Pentium´s compatibility, performance, organization, and development process are also described. The compiler technology developed with the Pentium microprocessor, which includes machine-independent optimizations common to current high-performance compilers, such as inlining, unrolling, and other loop transformations, is reviewed.<>

Keywords

computer architecture; microprocessor chips; pipeline processing; program compilers; BiCMOS technology; Pentium CPU; branch prediction; compatibility; compiler technology; inlining; loop transformations; machine-independent optimizations; pipelining; superscalar execution; unrolling; Application software; BiCMOS integrated circuits; CMOS technology; Central Processing Unit; Clocks; Computer architecture; Frequency; Microprocessors; Pipeline processing; Registers;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.216745

Filename

216745