Title :
Simultaneous routing and buffering in SOC floorplan design
Author :
Fang, J.P. ; Tong, Y.-S. ; Chen, S.J.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
An EDA tool to deal with the problems of routing and buffer-insertion in system-on-chip floorplanning simultaneously is developed. This routing and buffering tool mainly consists of a Manhattan routing (MR) algorithm and a maze-based between-buffer routing algorithm. Since the processing speed of its MR is very fast, this tool can be integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution.
Keywords :
VLSI; circuit layout CAD; system-on-chip; EDA tool; Manhattan routing algorithm; SOC floorplan design; Simultaneous routing; buffer insertion tool; iterative floorplanning algorithm, VLSI technology;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
DOI :
10.1049/ip-cdt:20040072
