Title :
Area-optimised registers using a folded PLA
Author :
Huertas, J.L. ; Quintana, J.M. ; Avedillo, M.J.
Author_Institution :
Dept. de Electron. y Electromagn., Fac. de Fisica, Sevilla Univ., Spain
fDate :
2/1/1990 12:00:00 AM
Abstract :
A method for implementing flip-flops using a folded PLA in a feedback connection is proposed. The new approach is shown to give effective circuits in terms of silicon area
Keywords :
cellular arrays; circuit layout; flip-flops; integrated logic circuits; logic arrays; logic design; shift registers; chip area-reduction; circuit layout; feedback connection; finite state machine synthesis; flip-flops; folded PLA; logic design; programmable logic array; regular array folding;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings G
