Investigation of multilayer metallisation in a gate array device using cross-sectional transmission electron microscopy

Author

Gong, S.F. ; Hentzell, H.T.G. ; Robertsson, A. ; Radnoczi, G.

Author_Institution

Dept. of Phys. & Meas. Technol., Linkoping Univ., Sweden

Volume

137

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

53

Lastpage

56

Abstract

Cross-sectional transmission electron microscopy (XTEM) was used to investigate structures of a multilayer of an integrated circuit. Microstructures of thin films, interfaces, interconnections, step coverage and dislocations in the device were revealed. Good step coverage was observed when polyimide was used as an insulator between two metal lasers. The results indicate that, with a proper technique of sample preparation, XTEM can be utilised as a unique way to characterise cross-sectional structures of very large scale integrated circuits

Keywords

VLSI; inspection; integrated circuit technology; logic arrays; metallisation; transmission electron microscope examination of materials; VLSI inspection; cross-sectional TEM; dislocations; gate array device; insulator; interconnections; interfaces; multilayer metallisation; polyimide; sample preparation; step coverage; thin film microstructure; transmission electron microscopy; very large scale integrated circuits;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings G

Publisher

iet

ISSN

0956-3768

Type

jour

Filename

217042