Limitation of the signal pin density on wiring boards

A practical limit of the signal pin density on wiring boards is investigated from the wireability point of view. The wireability problem can be expressed as a supply and demand model of two resources, i.e. wiring channels and via-holes. The limit of the signal pin density is assumed to be determined by the shortage of either of these two resources. As a measure of pin density, the average distance between adjacent signal pins, s_T, is introduced. The practical limit of s_T is estimated by analyzing the actual product data and experimental data. The lower bound of s_T, normalized by the grid spacing, can range from 1.5 to 2.0. These results are applied as a guideline to estimate the footprint area per LSI, and to do design tradeoffs among different packaging technologies such as multichip modules (MCM)