مرکز منطقه ای اطلاع رساني علوم و فناوري - Parallel cellular floating-point multiplier

DocumentCode :

907771

Title :

Parallel cellular floating-point multiplier

Author :

Fr¿¿con, L.

Author_Institution :

INSA, DÃ©partement Informatique, Villeurbanne, France

Volume :

Issue :

fYear :

1970

Firstpage :

226

Lastpage :

228

Abstract :

A cell is defined as a modified full adder. Such a cell allows the design of a multiplier, which handles signed floating point numbers.

Keywords :

adders; cellular arrays;

fLanguage :

English

Journal_Title :

Electronics Letters

Publisher :

iet

ISSN :

0013-5194

Type :

jour

DOI :

10.1049/el:19700158

Filename :

4234649

Link To Document :