Title :
My-box representation for faulty CMOS circuits
Author :
Chen, J.E. ; Lee, C.-L. ; Shen, W.-Z.
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
fDate :
6/1/1990 12:00:00 AM
Abstract :
A new logic element, My-box, is proposed to model the line faults (stuck-at-1 and stuck-at-0) and the transistor faults (stuck-on and stuck-open) of CMOS circuits, which consist of fully CMOS logic, pseudo NMOS logic, dynamic CMOS logic, clocked CMOS (C2MOS) logic, CMOS domino logic and NORA CMOS logic. It can also be used to model the faults and the functions of a transmission gate logic. A procedure is described to transform a transistor level CMOS circuit to a gate-level equivalent circuit which is composed of AND, OR and the My-box logic element. A fault collapsing procedure is also derived to determine the representative set of prime faults (RSPF) for the transformed gate-level circuit. By applying this procedure to ten benchmark circuits, the number of faults can be reduced to approximately 15% of the original total faults, if the ten benchmark circuits are implemented in the fully CMOS logic
Keywords :
CMOS integrated circuits; equivalent circuits; fault location; integrated circuit testing; integrated logic circuits; logic testing; C2MOS; My-box logic element; My-box representation; NORA; clocked CMOS; domino logic; dynamic CMOS logic; fault collapsing procedure; fault modelling; faulty CMOS circuits; fully CMOS logic; gate-level equivalent circuit; line faults; logic element; prime faults; pseudo NMOS logic; transistor faults; transistor level circuit transformation; transmission gate logic;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings G
