DocumentCode
907894
Title
Generation of ordered subcircuits for an automatic sizing program
Author
Howard, D. ; Walczowski, L.T. ; Waller, W.A.J. ; Smith, M.H.
Author_Institution
Electron. Eng. Labs., Kent Univ., Canterbury, UK
Volume
137
Issue
4
fYear
1990
fDate
8/1/1990 12:00:00 AM
Firstpage
315
Lastpage
318
Abstract
The design of increasingly complex integrated circuits requires synthesis tools rather than analysis tools. A tool that calculates transistor sizes is useful both to design a new circuit and to move an existing design to another process. The paper describes an algorithm that can be used in such a program to structure an otherwise unstructured array of unsized transistors in a CMOS digital circuit. This structure is related to the functionality of the circuit, so that the sizing model is provided with all the information required. The paper then goes on to discuss how the `subcircuits´ were ordered so that they could be sized, taking the necessary factors into account
Keywords
CMOS integrated circuits; circuit CAD; digital integrated circuits; CMOS digital circuit; automatic sizing program; functionality; ordered subcircuits; synthesis tools; transistor sizes; unsized transistors; unstructured array;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings G
Publisher
iet
ISSN
0956-3768
Type
jour
Filename
217080
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