Title :
Threshold shift of NMOS transistors due to high energy arsenic source/drain implantation
Author :
Sabine, K.A. ; Amaratunga, G.A.J. ; Evans, A.G.R.
Author_Institution :
University of Southampton, Department of Electronics and Information Engineering, Southampton, UK
fDate :
6/1/1985 12:00:00 AM
Abstract :
NMOS transistors using high-energy source/drain implantation have been found to have negative threshold shifts. These shifts are shown to be due to arsenic penetration of the polysilicon gate. An implant model of the three-layer structure has been used to predict the threshold shift, and good agreement is found with experimental results.
Keywords :
CMOS integrated circuits; ion implantation; semiconductor device models; As implant; NMOS transistors; high-energy source/drain implantation; implant model; n-channel device; n-well CMOS process; three-layer structure; threshold shift;
Journal_Title :
Solid-State and Electron Devices, IEE Proceedings I
DOI :
10.1049/ip-i-1.1985.0033
