• DocumentCode
    908044
  • Title

    Threshold shift of NMOS transistors due to high energy arsenic source/drain implantation

  • Author

    Sabine, K.A. ; Amaratunga, G.A.J. ; Evans, A.G.R.

  • Author_Institution
    University of Southampton, Department of Electronics and Information Engineering, Southampton, UK
  • Volume
    132
  • Issue
    3
  • fYear
    1985
  • fDate
    6/1/1985 12:00:00 AM
  • Firstpage
    163
  • Lastpage
    166
  • Abstract
    NMOS transistors using high-energy source/drain implantation have been found to have negative threshold shifts. These shifts are shown to be due to arsenic penetration of the polysilicon gate. An implant model of the three-layer structure has been used to predict the threshold shift, and good agreement is found with experimental results.
  • Keywords
    CMOS integrated circuits; ion implantation; semiconductor device models; As implant; NMOS transistors; high-energy source/drain implantation; implant model; n-channel device; n-well CMOS process; three-layer structure; threshold shift;
  • fLanguage
    English
  • Journal_Title
    Solid-State and Electron Devices, IEE Proceedings I
  • Publisher
    iet
  • ISSN
    0143-7100
  • Type

    jour

  • DOI
    10.1049/ip-i-1.1985.0033
  • Filename
    4643921
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=908044