DocumentCode :
908051
Title :
Optimal design and sequential analysis of VLSI testing strategy
Author :
Yu, Phillip S. ; Krishna, C.M. ; Lee, Yann-Hang
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Volume :
37
Issue :
3
fYear :
1988
fDate :
3/1/1988 12:00:00 AM
Firstpage :
339
Lastpage :
347
Abstract :
A method for determining the optimal testing period and measuring the production yield is discussed. With the increased complexity of VLSI circuits, testing has become more costly and time-consuming. The design of a testing strategy, which is specified by the testing period based on the coverage function of the testing algorithm, involves trading off the cost of testing and the penalty of passing a bad chip as good. The optimal testing period is first derived, assuming the production yield is known. Since the yield may not be known a priori, an optimal sequential testing strategy which estimates the yield based on ongoing testing results, which in turn determines the optimal testing period, is developed next. Finally, the optimal sequential testing strategy for batches in which N chips are tested simultaneously is presented. The results are of use whether the yield stays constant or varies from one manufacturing run to another
Keywords :
VLSI; fault tolerant computing; integrated circuit testing; VLSI testing strategy; coverage function; optimal design; production yield; sequential analysis; Automatic test pattern generation; Automatic testing; Circuit testing; Cost function; Manufacturing processes; Production; Sequential analysis; Signal generators; Test pattern generators; Very large scale integration;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.2171
Filename :
2171
Link To Document :
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