Title :
Testing of interconnection circuits in wafer-scale arrays
Author_Institution :
Dept. of Comp. Sci., Minnesota Univ., Minneapolis, MN, USA
fDate :
12/1/1990 12:00:00 AM
Abstract :
An efficient testing algorithm for interconnection circuits, including programmable switches and data links in wafer-scale reconfigurable arrays is presented. Faulty programmable switches or data links are eliminated by finding fault-free paths in the switch grid obtained by isolating all computing units from the rest of a reconfigurable array. No internal test points are assumed. The algorithm is shown to achieve very high performance, even if cell yield is low
Keywords :
VLSI; integrated circuit testing; logic arrays; logic testing; systolic arrays; Monte Carlo simulation; cell yield; data links; fault-free paths; interconnection circuits; programmable switches; reconfigurable array; switch grid; systolic arrays; testing algorithm; wafer-scale arrays; wafer-scale reconfigurable arrays;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings G
