An analog CMOS chip set for neural networks with arbitrary topologies

Author

Lansner, John A. ; Lehmann, Torsten

Author_Institution

Electron. Inst., Tech. Univ. of Denmark, Lyngby, Denmark

Volume

4

Issue

3

fYear

1993

fDate

5/1/1993 12:00:00 AM

Firstpage

441

Lastpage

444

Abstract

An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4×4 matrix-vector multiplier with variable, 10-b resolution matrix elements. The propagation delay of the test chips was measured to 2.6 μs per layer

Keywords

CMOS integrated circuits; analogue processing circuits; neural chips; 2.6 mus; ANN; analog CMOS chip set; arbitrary topologies; cascadable chips; hyperbolic tangent activation functions; matrix elements; matrix-vector multiplier; neural networks; neuron chip; parasitic lateral bipolar transistors; propagation delay; synapse chip; Artificial neural networks; Bipolar transistors; MOSFETs; Network topology; Neural networks; Neurofeedback; Neurons; Testing; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Neural Networks, IEEE Transactions on

Publisher

ieee

ISSN

1045-9227

Type

jour

DOI

10.1109/72.217186

Filename

217186