DocumentCode
909978
Title
Constant-G m rail-to-rail common-mode range input stage with minimum CMRR degradation
Author
Duque-Carrillo, J. Francisco ; Valverde, José M. ; Pérez-Aloe, Raquel
Author_Institution
Dept. of Electron. e Ing. Electromecanica, Univ. de Extremadura, Badajoz, Spain
Volume
28
Issue
6
fYear
1993
fDate
6/1/1993 12:00:00 AM
Firstpage
661
Lastpage
666
Abstract
The inherent drawbacks associated with CMOS amplifiers with rail-to-rail input common-mode range (CMR) are addressed. It is shown how they impact on the amplifier and limit its performance. An input stage, suitable to be incorporated in the design of any amplifier topology with extended input range, is introduced. By controlling the bias current level as a function of the input common-mode voltage, the input stage provides simultaneously an almost constant total transconductance and over 18 dB of common-mode rejection ratio (CMRR) improvement in comparison to the classical approach with just 5 V of total supply voltage. Experimental results obtained from the evaluation of a prototype chip fabricated in a standard CMOS p-well process with 2-μm feature size are given
Keywords
CMOS integrated circuits; amplifiers; linear integrated circuits; 2 micron; 5 V; CMOS amplifiers; CMOS p-well process; CMRR; IC; bias current level; common-mode; common-mode rejection ratio; constant total transconductance; input common-mode voltage; minimum CMRR degradation; monolithic type; rail-to-rail; range input stage; CMOS technology; Degradation; Differential amplifiers; Prototypes; Rail to rail amplifiers; Rail to rail inputs; Signal processing; Topology; Transconductance; Voltage control;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.217980
Filename
217980
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