• DocumentCode
    910059
  • Title

    A Simple FASTBUS Multiple Segment Implementation

  • Author

    Anderson, J. ; Farr, W. ; Napier, T. ; Roush, R. ; Yost, B.

  • Author_Institution
    LeCroy Corporation, Spring Valley, NY 10977
  • Volume
    33
  • Issue
    1
  • fYear
    1986
  • Firstpage
    804
  • Lastpage
    807
  • Abstract
    A simple FASTBUS multiple segment architecture has been implemented. Data transfer rates from the front end segments of up to 5 Mwords/sec have been measured. The implementation requires a LeCroy 1821 SM/I module and its accessory 1821/ECL interface card in each front end segment and a LeCroy 1892 FASTBUS memory in the MASTER segment. Data transfer does not require intervention by the HOST. Front end segment control is provided by the SM/I port of the 1892. Each 1892 can control up to 16 front end segments.
  • Keywords
    Broadcasting; CAMAC; Communication system control; Degradation; Fastbus; Memory management; Registers; Samarium; Signal generators; Springs;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.1986.4337221
  • Filename
    4337221
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=910059