Title :
A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator
Author :
Wu, Chung-Yu ; Chou, Chung-Yun
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
3/1/2004 12:00:00 AM
Abstract :
A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 μm CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.
Keywords :
CMOS integrated circuits; digital signal processing chips; quadrature phase shift keying; radio receivers; wireless LAN; 1.8 V; 22.4 mW; 5 GHz; CMOS double-quadrature receiver; image rejection; one-stage RLC phase shifter; power dissipation; quadrature RF signals; receiver chip; single-stage quadrature generator; voltage supply; wireless LAN; CMOS technology; Filters; Frequency; Low-noise amplifiers; Noise figure; Phase shifters; RLC circuits; Signal generators; Signal to noise ratio; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2003.822779
