Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS

A general procedure to size an inverter which drives a given capacitance load and which has precise pull-up and pull-down delays is discussed. This procedure is an iterative combination of a Newton-Raphson numerical method used to size the transistors, and ADVICE simulations to extract parameters used in the delay model for the inverter. The numerical method makes it possible to satisfy the delay constraints precisely, while ADVICE simulations ensure accuracy. This device-sizing procedure is then used to determine the sizes of inverters in two paths, one consisting of two inverters and the other three, each driving an arbitrary capacitive load, such that the complementary output of the two paths has minimal skew and pulsewidth distortion irrespective of the processing variations. A fully automatic procedure to achieve this requires only four ADVICE simulations and takes about four minutes of CPU time on an AMDAHL-5870 computer. The circuit designed by this procedure also has a very small skew and pulsewidth distortion with temperature variation with V_DD variation, and with the input rise and fall-time variations