• DocumentCode
    911064
  • Title

    Optimizing a superscalar machine to run vector code

  • Author

    Weiss, Shlomo

  • Author_Institution
    Dept. of Electr. Eng. & Syst., Tel Aviv Univ., Israel
  • Volume
    1
  • Issue
    2
  • fYear
    1993
  • fDate
    5/1/1993 12:00:00 AM
  • Firstpage
    73
  • Lastpage
    83
  • Abstract
    A streamlined vector architecture and the IBM superscalar RISC System/6000 are discussed. It is shown, step-by-step, how each handles the same program. The factors that let vector machines outperform the RS/6000 are identified. Several extensions to the RS/6000 architecture that could help it attain vector-level performance on code with long vectors are proposed.<>
  • Keywords
    parallel processing; performance evaluation; reduced instruction set computing; vector processor systems; IBM superscalar RISC System/6000; streamlined vector architecture; superscalar machine optimisation; vector code; vector-level performance; Clocks; Counting circuits; Delay; Floating-point arithmetic; Logic; Read-write memory; Reduced instruction set computing; Registers; Vector processors;
  • fLanguage
    English
  • Journal_Title
    Parallel & Distributed Technology: Systems & Applications, IEEE
  • Publisher
    ieee
  • ISSN
    1063-6552
  • Type

    jour

  • DOI
    10.1109/88.218177
  • Filename
    218177
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=911064