Title :
Modeling of gate oxide shorts in MOS transistors
Author_Institution :
Carnegie-Mellon Univ., Pittsburgh, PA
fDate :
3/1/1989 12:00:00 AM
Abstract :
A unified approach is proposed for modeling gate oxide shorts in MOS transistors using lumped-element models. These models take into account the possible structure of gate oxide short and the resulting changes that affect the I-V characteristics of MOS transistors. They can be used with the circuit simulator to predict the performance degradation of the VLSI circuit with gate oxide shorts. Demonstrated examples of models show close agreement with the experimental data
Keywords :
VLSI; insulated gate field effect transistors; semiconductor device models; I-V characteristics; MOS transistors; VLSI circuit; circuit simulator; gate oxide shorts; lumped-element models; performance degradation; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit modeling; MOSFETs; Predictive models; Semiconductor device modeling; Semiconductor process modeling; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
