Title :
Optimisation of VDMOS power transistors for minimum on-state resistance
Author :
Davies, J.T. ; Walker, P. ; Nuttall, K.I.
Author_Institution :
University of Liverpool, Department of Electrical Engineering and Electronics, Liverpool, UK
fDate :
6/1/1987 12:00:00 AM
Abstract :
A 2-dimensional numerical simulation program has been applied to the power VDMOS structure to determine design guidelines for minimum specific on-state resistance subject to a given breakdown voltage requirement. The entire cell has been modelled to take full account of contributions from the inversion and accumulation layers as well as the effect of cell spacing on the breakdown voltage. Optimised cell width, epitaxial thickness and doping concentration are presented for a range of breakdown voltages. The results show that the optimum body diffusion spacing increases with the breakdown voltage rating up to approximately 400 V, giving an approximately linear relationship between the on-state resistance-area product and breakdown voltage for a constant body width of 15 ¿m.
Keywords :
insulated gate field effect transistors; power transistors; 15 micron; 2-dimensional numerical simulation program; 400 V; VDMOS power transistors; accumulation layers; breakdown voltage requirement; cell spacing; cell width; design guidelines; doping concentration; epitaxial thickness; inversion; minimum on-state resistance; optimum body diffusion spacing;
Journal_Title :
Solid-State and Electron Devices, IEE Proceedings I
DOI :
10.1049/ip-i-1.1987.0015
