• DocumentCode
    912184
  • Title

    Logic Partitioning for Minimizing Gate Arrays

  • Author

    Palesko, Chet A. ; Akers, Lex A.

  • Author_Institution
    Honeywell Large Information Systems Division, Phoenix, AZ, USA
  • Volume
    2
  • Issue
    2
  • fYear
    1983
  • fDate
    4/1/1983 12:00:00 AM
  • Firstpage
    117
  • Lastpage
    121
  • Abstract
    This paper describes a procedure for partitioning logic to minimize the number of gate arrays required to implement the logic. The procedure consists of three algorithms to perform initial, iterative, and interactive logic partitioning. Results are presented using three different logic circuits ranging in size from 14 000 gates to 26 000 gates.
  • Keywords
    Costs; Design automation; Integrated circuit interconnections; Iterative algorithms; Logic arrays; Logic circuits; Logic design; Logic gates; Partitioning algorithms; Programmable logic arrays;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1983.1270028
  • Filename
    1270028
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=912184