Simulation of highvoltage power switching transistors under forced gain and inductive load turn-off conditions

Computer simulation under static conditions is performed to compare gain and saturation voltage with collector current for a power switching transistor for which process data had been measured. The transistor simulation is then carried out for a range of static solutions to generate look-up tables forming the circuit CAD model. A circuit analysis program is then used to examine the variation of current density with time within the transistor. Comparing instantaneous current density and collector-emitter voltage with a static solution of the ionisation integral under high current density conditions allows prediction of second breakdown under reverse base drive with inductive load. Computer results are compared with measured data.