Title :
Vectorized LU Decomposition Algorithms for Large-Scale Circuit Simulation
Author :
Yamamoto, Fujio ; Takahashi, Sakae
Author_Institution :
Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo, Japan
fDate :
7/1/1985 12:00:00 AM
Abstract :
Proposed here are two kinds of vectorized LU decomposition algorithms for an unstructured sparse matrix arising from large scale circuit simulation. Either algorithm implemented on our supercomputer S810 improves efficiency 11 to 82 times for LU decomposition and 2.1 to 8.9 times in total simulation, as compared with a conventional algorithm. Both algorithms detect operational parallelism in the irregularity of a matrix. While one of them limits the scope of parallelism detection to each set of consecutive columns so as to take advantage of the dense matrix method applicable to the lower right corner, the other tries to locate parallelism all over the matrix in every step without switching to a faster linear-index vector.
Keywords :
Circuit simulation; Computational modeling; Computer simulation; Large-scale systems; MOSFETs; Matrix decomposition; Parallel processing; Sparse matrices; Vector processors; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.1985.1270119