Goal-oriented subgraph isomorphism technique for IC device recognition

The paper describes a programmable mask analysis system to check technology rules and extract circuits in a low cost computing environment. The mask verification language (MVL) programmer is only concerned with how a device is fabricated and not with how it is actually recognised. The system includes an optimising MVL compiler that removes redundant mask operations, and efficiency is thereby maximised by minimising the volume of mask data that must be processed. A geometry processor reduces the mask set to a set of topologically interrelated entities called features. These features are analysed to recognise instances of devices using a goal oriented sub-graph isomorphism algorithm. Conventionally, the execution times of graph isomorphism algorithms are related polynomially to the problem size. However, by careful organisation of the database, and by imposing certain rules on the structure of the MVL, execution times that are almost linear are obtained.