DocumentCode :
913250
Title :
A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays
Author :
Terai, Masayuki
Author_Institution :
LSI Research and Development Laboratory, Mitsubishi Electric Corporation, Itami, Japan
Volume :
4
Issue :
3
fYear :
1985
fDate :
7/1/1985 12:00:00 AM
Firstpage :
329
Lastpage :
336
Abstract :
The channel router, which routes a rectangular channel with two rows of terminals along its top and bottom sides, is extensively used for the automatic routing of gate arrays. It is well known that in this routing method the routing can not be performed when the vertical constraint graph contains cycles. This paper deals with the problem of eliminating cycles in the vertical constraint graph by interchanging the nets assigned to logically equivalent terminals before channel routing. A heuristic algorithm is proposed for this problem. This algorithm yields a locally optimum assignment of nets to terminals, in the sense that the number of independent cycles in the vertical constraint graph of a resultant assignment can not be reduced by interchanging any pair of the nets assigned to logically equivalent terminals. Furthermore, in order to speed up the operation of this algorithm, it is shown that the checking as to whether or not the number of independent cycles in the vertical constraint graph is reduced can be done by noting only its subgraph, when a pair of nets assigned to logically equivalent terminals are interchanged. Experimental results have indicated that this proposed algorithm is efficient.
Keywords :
Design automation; Electric resistance; Heuristic algorithms; Large scale integration; Research and development; Routing; Terminology;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.1985.1270129
Filename :
1270129
Link To Document :
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