DocumentCode :
913273
Title :
A Switch-Level Timing Verifier for Digital MOS VLSI
Author :
Ousterhout, John K.
Author_Institution :
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, USA
Volume :
4
Issue :
3
fYear :
1985
fDate :
7/1/1985 12:00:00 AM
Firstpage :
336
Lastpage :
349
Abstract :
Crystal is a timing verification program for digital nMOS and CMOS circuits. Using the circuit extracted from a mask set, the program determines the length of each clock phase and pinpoints the longest paths. Crystal can process circuits with about 40 000 transistors in about 20-30 min of VAX-11/780 CPU time. The program uses a switch-level approach in which the circuit is decomposed into chains of switches called stages. A depth-first search, with pruning, is used to trace out stages and locate the critical paths. Bidirectional pass transistor arrays are handled by having the designer tag such structures with flow control information, which is used by Crystal to avoid endless searches. Delays are computed on a stage-by-stage basis, using a simple resistor-switch model based on rise-time ratios (a measure of how fully turned-on the transistors in the stage are). The delay modeler executes 10 000 times as fast as SPICE, yet produces delay estimates that are typically within 10 percent of SPICE for digital circuits.
Keywords :
CMOS digital integrated circuits; Central Processing Unit; Clocks; Delay estimation; MOS devices; SPICE; Switches; Switching circuits; Timing; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.1985.1270130
Filename :
1270130
Link To Document :
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