Correlation of Total Dose Damage in Capacitors and Transistors to 1.25 Micron Integrated Circuits

Parametric data taken from the irradiation of transistors and capacitors has been correlated with integrated circuit response in 1.25 micron technology. Data taken on worst case biased test transistors (+ 5 V static gate bias for n-channel, O V p-channel) accurately predicts worst case propagation delay changes in an irradiated ALU. Dynamically biased test transistors successfully model the access time delay of a RAM and a ROM after irradiation. The results indicate that worst case bias conditions for an integrated circuit during irradiation depend on the pathway measured and that test transistors provide a better measure of worst case total dose hardness of an IC rather than direct irradiation of the part itself.