• DocumentCode
    913585
  • Title

    Neutron-Induced Latch-Up Immunity in Metal Gate CMOS Integrated Circuits

  • Author

    Barnes, C.E. ; Rollins, J.G. ; Hachey, D.

  • Author_Institution
    The Aerospace Corp., El Segundo, CA 90245
  • Volume
    34
  • Issue
    6
  • fYear
    1987
  • Firstpage
    1769
  • Lastpage
    1774
  • Abstract
    Neutron-induced latch-up immunity has been studied in metal gate CMOS integrated circuits as a function of neutron fluence by measuring both the current gain products (beta product) of parasitic NPN and PNP transistors, and the flash x-ray latch-up thresholds prior to and following irradiation and subsequent stabilization anneal. Correlations between the actual latch-up thresholds and the measured beta products are established for the three part types investigated. These correlations indicate that the measurement of beta products on judiciously chosen parasitic transistors is a viable technique for estimating latch-up susceptibility when the observed margin is substantial.
  • Keywords
    Annealing; CMOS integrated circuits; CMOS technology; Current measurement; Electronic circuits; Gain measurement; Integrated circuit measurements; Integrated circuit reliability; Neutrons; Radiation hardening;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.1987.4337552
  • Filename
    4337552