An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design

An integrated and efficient approach is developed for automated statistical circuit design. One major problem in statistical circuit design for MOS VLSI is the prohibitively expensive computational requirements. The objective is to find realistic, accurate, and efficient solutions for use in the MOS VLSI design area. An automated statistical characterization system has been developed to characterize a large number of MOS devices to obtain statistical information on device parameters. A statistical model for MOS VLSI circuits has been developed in which only the interdie variations are considered, since they are much larger than the local intradie variations. Therefore, the set of statistical variables are different from the set of design parameters, and this leads to a resolution of the problem of dimensionality associated with statistical design. In this statistical model, variations in device length and width, oxide capacitance, and flat band voltage, have been shown to be the principal process factors responsible for the statistical variation of device characteristics. A scalable MOS model has been developed to represent changes in the device model parameters as functions of these principal factors. This accurate and simple statistical modeling approach uses only four statistical variables, and thus permits computationally efficient statistical parametric yield estimation (SPYE). The direct approach for transient sensitivity computation has been implemented in SPICE to allow very efficient computation of performance function sensitivities. An efficient technique for computing the yield gradient using the SPYE and transient sensitivity results is discussed and an example is presented to demonstrate its use in parametric yield optimization.