• DocumentCode
    913795
  • Title

    Algorithms and Software Tools for IC Yield Optimization Based on Fundamental Fabrication Parameters

  • Author

    Styblinski, M.A. ; Opalski, L.J.

  • Author_Institution
    Department of Electrical Engineering, Texas A&M University, College Station, TX, USA
  • Volume
    5
  • Issue
    1
  • fYear
    1986
  • fDate
    1/1/1986 12:00:00 AM
  • Firstpage
    79
  • Lastpage
    89
  • Abstract
    Algorithms, software tools and the relevant methodology for production yield optimization with respect to fundamental technological parameters of the IC manufacturing process (such as diffusion times and temperatures) and element layout mask dimensions are discussed. The tools developed include: STOCH-PAC--a package of new yield optimization and yield gradient estimation algorithms based on Stochastic Approximation approach and the Method of Random Perturbations; YIELD-PAC - a package of yield evaluation subroutines providing an interface to SPICE-PAC circuit simulation package; FABPAC - an interface to the FABRICS statistical process simulator; and IRIS (Interactive Restructurable Interface System)--a flexible user interface for efficient data manipulation, creation of different design tasks and macrotasks, restructuring the set of active subroutines, etc. These tools have been integrated into the TOY (Technological Optimization of Yield) program. Examples of yield optimization with respect to process parameters and layout dimensions using TOY are given.
  • Keywords
    Circuit simulation; Design optimization; Fabrication; Integrated circuit layout; Manufacturing processes; Optimized production technology; Packaging; Software algorithms; Software tools; Temperature;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1986.1270179
  • Filename
    1270179