A Methodology for Worst-Case Analysis of Integrated Circuits

Author

Nassif, Sani R. ; Strojwas, Andrzej J. ; Director, Stephen W.

Author_Institution

Department of Electrical and Computer Engineering, Research Center for Computer-Aided Design, Carnegie-Mellon University, Pittsburgh, PA, USA

Volume

5

Issue

1

fYear

1986

fDate

1/1/1986 12:00:00 AM

Firstpage

104

Lastpage

113

Abstract

Worst-case analysis is one of the most often used techniques for verifying that the sensitivity of integrated circuit (IC) performances to changes in manufacturing conditions is minimized. However, worst-case analysis is often carried out in terms of a correlated set of parameters, which results in a design that is unnecessarily pessimistic. This paper presents a new approach to the worst-case analysis of integrated circuits that results in more realistic estimates of variations in device and circuit performances. In particular, worst-case analysis is performed in terms of a set of statistically independent process disturbances. A software package for worst-case analysis is described and illustrated by a number of examples. The results of the proposed worst-case analysis method are compared to Monte Carlo simulations.

Keywords

Circuit analysis; Circuit simulation; Delay lines; Fluctuations; Integrated circuit manufacture; Manufacturing processes; Performance analysis; Performance evaluation; Power dissipation; Software packages;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.1986.1270181

Filename

1270181