DocumentCode
914072
Title
VLSI Simulation and Data Abstractions
Author
Katzenelson, Jacob ; Weitz, Eliezer
Author_Institution
Department of Electrical Engineering, Technion-Israel Institute of Technology, Haifa, Israel
Volume
5
Issue
3
fYear
1986
fDate
7/1/1986 12:00:00 AM
Firstpage
371
Lastpage
378
Abstract
Multilevel simulation is a technique for specifying and testing VLSI chip designs. This paper compares three methods of implementing such simulators: (a) Programming using a high level language that does not have data abstraction, e.g., Pascal. (b) Programming with procedure oriented data abstractions as in Simula [3] or CLU [4]. (c) Programming with enhanced C´s (EC) [2] data abstractions that are macro oriented. LIST -- a generator for simulation programs based on the data abstraction technique is described briefly. It is concluded that the use of data abstractions offers structure, hierarchy and simplicity. The use of EC has the additional advantage of run-time efficiency.
Keywords
Chip scale packaging; Computational modeling; Hardware; Jacobian matrices; Logic design; Logic devices; Process design; Runtime; Testing; Very large scale integration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.1986.1270206
Filename
1270206
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