• DocumentCode
    914099
  • Title

    Collecting Data About Logic Simulation

  • Author

    Chamberlain, Roger D. ; Franklin, M.A.

  • Author_Institution
    Department of Computer Science and Electrical Engineering, Washington University, St. Louis, MO, USA
  • Volume
    5
  • Issue
    3
  • fYear
    1986
  • fDate
    7/1/1986 12:00:00 AM
  • Firstpage
    405
  • Lastpage
    412
  • Abstract
    Design of high-performance hardware and software-based gate-switch-level logic simulators requires knowledge about the logic simulation process itself. Unfortunately, little data is publicly available concerning key aspects of this process. An example of this is the lack of published empirical measurements relating to the time distribution of events generated by such simulators. This paper presents a gate-switch-level logic simulator lsim which is oriented towards the collection of data about the simulation process. The basic components of lsim are reviewed, and its relevant data gathering facilities are discussed. An example is presented which illustrates the use of lsim in gathering data on event distributions and on communications requirements under alternative logic circuit partitionings.
  • Keywords
    Circuit faults; Circuit simulation; Computational modeling; Costs; Discrete event simulation; Hardware; Logic design; Logic gates; Logic testing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1986.1270209
  • Filename
    1270209