DocumentCode :
914293
Title :
Parsing electronic circuits in a logic grammar
Author :
Tanaka, Takushi
Author_Institution :
Dept. of Comput. Sci., Fukuoka Inst. of Technol., Japan
Volume :
5
Issue :
2
fYear :
1993
fDate :
4/1/1993 12:00:00 AM
Firstpage :
225
Lastpage :
239
Abstract :
Understanding circuits is a prerequisite for circuit design and trouble shooting. Circuit understanding by engineers is described as a process that starts with a structural analysis and then proceeds to a causal analysis. As a step toward automatic circuit understanding, a method for analyzing circuit structures is presented. In this method, a circuit is reviewed as a sentence and its elements as words. Circuit structures are defined by rules written in a logic grammar called definite clause set grammar (DCSG). Given circuits are decomposed into parse trees by the DCSG top-down parsing mechanism. These parse trees represent hierarchical structures of functional blocks. This representation is presented as one step in the process of automatic understanding of circuit structures
Keywords :
circuit analysis computing; formal logic; grammars; trees (mathematics); DCSG top-down parsing mechanism; automatic circuit understanding; causal analysis; circuit design; circuit structures; definite clause set grammar; functional blocks; hierarchical structures; logic grammar; parse trees; sentence; structural analysis; trouble shooting; words; Circuit analysis; Circuit simulation; Circuit synthesis; Computational modeling; Electronic circuits; Knowledge representation; Logic circuits; Logic programming; Natural languages; Voltage;
fLanguage :
English
Journal_Title :
Knowledge and Data Engineering, IEEE Transactions on
Publisher :
ieee
ISSN :
1041-4347
Type :
jour
DOI :
10.1109/69.219732
Filename :
219732
Link To Document :
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