DocumentCode :
914320
Title :
Synthesis and Optimization of Multilevel Logic under Timing Constraints
Author :
Bartlett, Karen ; Cohen, William ; De Geus, Aart ; Hachtel, Gary
Author_Institution :
Department of Electrical and Computer Engineering, University of Colorado at Boulder, Boulder, CO, USA
Volume :
5
Issue :
4
fYear :
1986
fDate :
10/1/1986 12:00:00 AM
Firstpage :
582
Lastpage :
596
Abstract :
The automation of the synthesis and optimization of combinational logic can result in savings in design time, significant improvements of the circuitry, and guarantee functional correctness. Synthesis quality is often measured in terms of the area of the circuit on the chip, which fails to take into account the timing constraints that might be imposed on the logic. This paper describes SOCRATES, a synthesis system capable of generating combinational logic in a given technology under user-defined timing constraints. We believe this system is the first to perform optimized, delay-constrained, multilevel synthesis into standard cell libraries. Applied to a large number of examples, the system has successfully traded off area versus delay and performs optimized, delay-constrained, multilevel synthesis into standard cell libraries.
Keywords :
Area measurement; Circuit synthesis; Combinational circuits; Constraint optimization; Delay; Design automation; Design optimization; Libraries; Logic design; Timing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.1986.1270229
Filename :
1270229
Link To Document :
بازگشت