• DocumentCode
    914441
  • Title

    A Systolic Design-Rule Checker

  • Author

    Kane, Rajiv ; Sahni, Sartaj

  • Author_Institution
    Daisy Systems, San Jose, CA, USA
  • Volume
    6
  • Issue
    1
  • fYear
    1987
  • fDate
    1/1/1987 12:00:00 AM
  • Firstpage
    22
  • Lastpage
    32
  • Abstract
    We develop a systolic design-rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design-rule check phase of chip design.
  • Keywords
    Design-Rule Checks; feature width; rectilinear geometries; spacing; systolic systems; Algorithm design and analysis; Chip scale packaging; Circuits; Complexity theory; Computer architecture; Design automation; Geometry; Logic; Routing; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1987.1270242
  • Filename
    1270242
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=914441