Title :
A Systolic Design-Rule Checker
Author :
Kane, Rajiv ; Sahni, Sartaj
Author_Institution :
Daisy Systems, San Jose, CA, USA
fDate :
1/1/1987 12:00:00 AM
Abstract :
We develop a systolic design-rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design-rule check phase of chip design.
Keywords :
Design-Rule Checks; feature width; rectilinear geometries; spacing; systolic systems; Algorithm design and analysis; Chip scale packaging; Circuits; Complexity theory; Computer architecture; Design automation; Geometry; Logic; Routing; Wire;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.1987.1270242
