Title :
Block-Level Hardware Logic Simulation Machine
Author :
Takasaki, Shigeru ; Sasaki, Tohru ; Nomizu, Nobuyoshi ; Koike, Nobhuiko ; Ohmori, Kenji
Author_Institution :
NEC Corporation, Fuchu City, Tokyo, Japan
fDate :
1/1/1987 12:00:00 AM
Abstract :
This paper describes a block-level hardware logic simulation machine. This is called a Hardware Logic Simulator (HAL). This paper first shows a block-level simulation method. Then, it overviews HAL hardware and software system configurations, and the simulation mechanism, and it estimates system performance. Finally, it discusses system applications and results. The paper also indicates that HAL has been successfully used.
Keywords :
Special-purpose hardware; block-level simulation; logic simulation; parallel processing; pipeline processing; Application software; Computational modeling; Design methodology; Digital systems; Discrete event simulation; Hardware; Large scale integration; Logic; Manufacturing; Prototypes;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.1987.1270245
