DocumentCode :
914610
Title :
A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach
Author :
Fujii, Takashi ; Horikawa, Hideya ; Kikuno, Tohru ; Yoshida, Noriyoshi
Author_Institution :
Faculty of Engineering, Hiroshima University, Higashi-Hiroshima, Japan
Volume :
6
Issue :
2
fYear :
1987
fDate :
3/1/1987 12:00:00 AM
Firstpage :
159
Lastpage :
164
Abstract :
In this paper, we present a new approach for the one-dimensional gate assignment problem. The original minimization problem is transformed into a restricted problem, and then a new heuristic algorithm is applied to it. The solution obtained by the algorithm is interpreted as a solution for the original problem. The whole process of the approach has been implemented and tested with various examples. Experimental results show that our approach can approximately produce optimum solutions.
Keywords :
Circuit testing; Design automation; Heuristic algorithms; Logic arrays; Logic circuits; Minimization methods; System testing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.1987.1270259
Filename :
1270259
Link To Document :
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