Title :
Monolithic SMPTE Time Code Reader LSI using Gate Array
Author :
Kobayashi, Ki-ichi ; Nakamura, Masashi ; Kokubun, Hideki ; Aida, Tahito ; Akechi, Kazuyuki ; Ohmachi, Satoru ; Kawashima, Tadashi
Author_Institution :
Electron Devices Research Division NHK Technical Reserch Laboratories
Abstract :
This paper describes an SMPTE time code reader LSI using gate arrays. The reader consists of two chips, i.e., a bit clock extracting chip, and a display interface chip. All circuits are designed with random logic gates.
Keywords :
Broadcasting; CMOS logic circuits; Clocks; Flip-flops; Large scale integration; Latches; Logic arrays; Logic circuits; Logic gates; Wiring;
Journal_Title :
Broadcasting, IEEE Transactions on
DOI :
10.1109/TBC.1983.266504
