• DocumentCode
    914819
  • Title

    Monolithic SMPTE Time Code Reader LSI using Gate Array

  • Author

    Kobayashi, Ki-ichi ; Nakamura, Masashi ; Kokubun, Hideki ; Aida, Tahito ; Akechi, Kazuyuki ; Ohmachi, Satoru ; Kawashima, Tadashi

  • Author_Institution
    Electron Devices Research Division NHK Technical Reserch Laboratories
  • Issue
    4
  • fYear
    1983
  • Firstpage
    135
  • Lastpage
    144
  • Abstract
    This paper describes an SMPTE time code reader LSI using gate arrays. The reader consists of two chips, i.e., a bit clock extracting chip, and a display interface chip. All circuits are designed with random logic gates.
  • Keywords
    Broadcasting; CMOS logic circuits; Clocks; Flip-flops; Large scale integration; Latches; Logic arrays; Logic circuits; Logic gates; Wiring;
  • fLanguage
    English
  • Journal_Title
    Broadcasting, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9316
  • Type

    jour

  • DOI
    10.1109/TBC.1983.266504
  • Filename
    4044341
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=914819