Title :
SIGMA: a VLSI systolic array implementation of a Galois field GF(2/sup m/) based multiplication and division algorithm
Author :
Kovac, Mario ; Ranganathan, N. ; Varanasi, Murali
Author_Institution :
Coll. of Electr. Eng., Zagreb Univ., Croatia
fDate :
3/1/1993 12:00:00 AM
Abstract :
Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. The design of efficient methods for Galois field arithmetic such as multiplication and division is critical for these applications. A new algorithm based on a pattern matching technique for computing multiplication and division in GF(2/sup m/) is presented. An efficient systolic architecture is described for implementing the algorithm which can produce a new result every clock cycle and the multiplication and division operations can be interleaved. The architecture has been implemented using 2- mu m CMOS technology. The chip yields a computational rate of 33.3 million multiplications/divisions per second.<>
Keywords :
CMOS integrated circuits; VLSI; digital arithmetic; multiprocessing systems; systolic arrays; 2 micron; CMOS; Galois field arithmetic; Galois fields; VLSI systolic array implementation; computational rate; cryptography; digital signal processing; division; error correcting codes; multiplication; pattern matching technique; systolic architecture; CMOS technology; Computer architecture; Cryptography; Design methodology; Digital signal processing; Error correction codes; Galois fields; Signal processing algorithms; Systolic arrays; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
