Pad Assignment for Power Nets in VLSI Circuits

This paper deals with the problem of single layer routing of power nets in building-block-style layout. It is assumed that power-supplying terminals are placed on the boundary of the chip and that each module within the chip has to be supplied by two or three different sources. The problem considered here is how to assign the power pads on the boundary of the chip so that their number is minimum while maintaining the planar routability of the power nets.