Hierarchical Loose Routing for Gate Arrays

In this paper, we present a new, quasi-parallel approach to the loose routing problem for gate array LSI design. It is based on a new modeling for the decomposition problem of each net using a compact net graph which maps sets of feed-throughs instead of individual ones. The loose routing is done by calculation of a minimum spanning tree in this net graph and by a proper embedding of the tree as a set of single-channel subnets and feed-throughs. Moreover, a hierarchical approach is proposed, leading to a quasi-parallel embedding of all nets. It also allows different routing priorities for single connections within multiterminal nets. The hierarchical loose routing concept presented here is implemented in the fully integrated gate array design system MEGA and has been successfully tested on several industrial design examples.